Testing of an integrated circuit (IC) chip is often limited by the function the chip is designed to perform during functional operation. This is especially true in the testing of unassembled chips of a three dimensional (3D) stacked chip system where the test is being performed on a circuit that is only partially complete, i.e., is not a fully integrated circuit. For example, a circuit in a 3D stacked chip system often traverses the interface between chips. These circuits are incomplete when the individual chips are unassembled, e.g., prior to connecting the chips to one another in a stack, such that testing is typically done only after assembling the chips are assembled in the stack. This practice, however, leads to higher yield loss since one faulty chip in an assembled chip stack may cause other good chips in the chip stack to be discarded. Additionally, testing of multiple devices requires individual connection with each device (e.g., chip, 3D assembly), requiring more fully integrated devices, and the time/cost associated with connecting to each device
Chip to chip stacking (e.g., stacked chip systems, 3D technology, etc.) utilizes through-silicon vias (TSVs), which are electrical contacts that extend through a substrate (e.g., silicon) and permit electrical connection from one side of the substrate to the other. Chip to chip stacking also utilizes Inner Stratum Input Output (ISIO), which are chip to chip connections. Chip to chip stacking also introduces the drive to provide Known Good Die (KGD) to the chip stack for the yield loss reason already described, and this drives performing as much testing on individual die (e.g., chips) as soon as possible in the manufacturing process which, in turn, increases wafer testing requirements to achieve KGD goals.
Interconnect and TSV density is trending in a direction that makes it more difficult to support KGD requirements of 3D technology. For example, the density of interconnects and TSVs (e.g., the number of elements per die area) can increase by sixteen-fold (16×) over the span of 2 to 3 years. This constant increase in interconnect and TSV density makes it increasingly difficult to perform wafer probe tests, and wafer probing of the ever-increasing number of elements may become untenable.
Manufacturing issues are also introduced by the inability to fully test a TSV with single sided wafer probing. Probe and equipment limitations do not support interconnect density scaling factors, and the constant scaling of these elements represents a technical challenge that may become cost prohibitive. ISIO testing is also difficult in that there is no access to ISIO instances off-chip for testability until the individual chips are assembled into stacks. Increasing instance counts and lower fault coverage of instances results in increasing fault occurrences, which results in increasing yield impacts. Without a mode for rework of assembled chip stacks, the delaying of TSV testing until package testing (e.g., after chip stack assembly) results in higher yield loss due to compounding of yield loss in multi-chip packaging.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.